With the advance of 1C technology, IC\’s complexity and performance grow rapidly, which give much challenge to the traditional methods or techniques.This paper presents a new test method-at-speed current testing based on analyzing the theories, characteristics and shortcomings of quiescent power supply current testing and dynamic current testing.The method of at-speed current testing combines this two current testing methods, applies two alternative vectors to circuits under test to enable the possibility for using a slow measurement and testing at a high frequency operation. By using it, the test can be done at the operation frequency of circuits under test, therefore results of the test can be more precise and this method can detect different types of faults.For this new method, this paper implements a test generation algorithm at gate level by means of counting only logical up-transitions based on Boolean process, and employing the Bayesian optimization algorithm, and makes some experiments on the ISCAS\’85 benchmark circuit to check its validity. SPICE simulation shows that tests generated by the algorithm can be observed either by ATE or a waveform sensor even if its operation frequency is much lower than that of ICs under test. The experiment results also illustrate the feasibility of the at-speed current testing scheme.To improve the efficiency of test generation, this paper proposes some techniques for fault collapsing, such as fault compression, fault simulation, and etc, for stuck-open faults, and their application to test generation for at-speed current testing. Experimental results show that by using the techniques, the number of faults to be tested for test generation decreases greatly.Besides fault collapsing, this paper also proposes some techniques, such as code collapsing, change of the ending rules to optimizing the test generation algorithm. Experiments of some examples demonstrate that the test generation efficiency is enhanced 200 times, and the fault coverage has little loss.

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